The diagram shows a simplified representation of the fetch stage of the fetch-decode-execute cycle. (a) Using the diagram, describe what happens at each of ...
Question 1 Report
The diagram shows a simplified representation of the fetch stage of the fetch-decode-execute cycle.
(a) Using the diagram, describe what happens at each of the four steps shown in the fetch stage. [4]
(b) After the fetch stage, the instruction must be decoded. Describe what happens during the decode stage. [2]
(c) Give two examples of instructions that the CPU might execute during the execute stage. [2]
(d) Explain the role of the address bus, data bus and control bus during the fetch-decode-execute cycle. [3]
Answer Details
(a) The four steps of the fetch stage are:
- Step 1: The address of the next instruction is copied from the Program Counter (PC) into the Memory Address Register (MAR). The PC holds the address; the MAR is the register that feeds the address bus. [1]
- Step 2: The address now held in the MAR is placed onto the address bus and sent to main memory. Simultaneously, a read control signal is sent along the control bus, telling memory to provide the contents at that address. [1]
- Step 3: The instruction stored at the specified memory address is fetched from memory and travels along the data bus into the Memory Data Register (MDR). The MDR now holds the instruction ready for decoding. [1]
- Step 4: The Program Counter is incremented by 1 (PC = PC + 1), so it now points to the address of the next instruction to be fetched in the following cycle. [1]
(b) During the decode stage, the Control Unit takes the instruction from the MDR and interprets (decodes) it. [1] It identifies the type of operation to be performed (e.g. arithmetic, data transfer, comparison) and determines which data or memory addresses are involved, then prepares the appropriate control signals to carry out the instruction during the execute stage. [1]
(c) Two examples of instructions that may be executed:
- The ALU performs an arithmetic calculation, such as adding two numbers together, and stores the result in the Accumulator (ACC). [1]
- Data held in the MDR is written to a specified memory address via the data bus, storing a result or value back into main memory. [1]
(d) The three system buses play distinct roles during the cycle:
- Address bus: carries the memory address from the MAR to main memory, specifying which location to read from or write to. [1]
- Data bus: carries the actual data or instructions between the CPU and memory in both directions (bidirectional). [1]
- Control bus: carries control signals such as read, write and clock signals that coordinate the operations of the CPU, memory and I/O devices. [1]
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