A student is investigating how the central processing unit (CPU) runs a program. The CPU contains a control unit (CU), an arithmetic logic unit (ALU), regis...
Question 1 Report
A student is investigating how the central processing unit (CPU) runs a program. The CPU contains a control unit (CU), an arithmetic logic unit (ALU), registers and a clock. A clock sends regular pulses so that operations occur in the correct sequence. The CPU communicates with memory and other hardware using buses. The diagram shows a simplified CPU system. The table represents part of a fetch–decode–execute cycle; the program counter (PC) initially contains 120 and the memory address register (MAR) initially contains 0. Assume that memory location 120 stores the instruction LOAD 45, which means “copy the data at address 45 into the accumulator”.
| Stage | PC | MAR | MDR | CIR | Accumulator |
|---|---|---|---|---|---|
| Start | 120 | 0 | — | — | 0 |
| 1 | 120 | (i) | — | — | 0 |
| 2 | 121 | 120 | (ii) | — | 0 |
| 3 | 121 | 120 | LOAD 45 | (iii) | 0 |
(a) State the full name of ALU. [1]
(b) Identify bus A. [1]
(c) Identify bus B. [1]
(d) Give the purpose of the control bus. [2]
(e) Complete cells (i), (ii) and (iii) in the table. [3]
(f) State the register that holds the address of the next instruction to be fetched. [1]
(g) Explain why the CPU clock is needed when a program is executed. [2]
(h) Give two tasks carried out by the control unit during instruction processing. [2]
(i) Convert the decimal address 45 to 8-bit binary. [2]
Answer Details
(a) ALU means Arithmetic Logic Unit [1].
(b) Bus A is the address bus [1].
(c) Bus B is the data bus [1].
(d) The control bus carries control signals or commands, such as read and write signals, between the CPU and memory [2].
(e) In stage 1, the PC value is copied to the MAR, so (i) is 120. Memory location 120 is read into the MDR, so (ii) is LOAD 45. It is copied into the CIR for decoding, so (iii) is LOAD 45 [3].
(f) The program counter (PC) holds the address of the next instruction to fetch [1].
(g) Clock pulses synchronise CPU operations, ensuring fetch, decode and execute happen in the correct order and at the correct times [2].
(h) The control unit decodes instructions and sends control signals to coordinate data movement and the fetch-decode-execute cycle [2].
(i) \(45=32+8+4+1\), so the 8-bit binary address is 00101101 [2].
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