Computer Architecture
Akopọ
Inside every computer is a single chip that does the actual thinking: the central processing unit. It does not work by magic but by repeating one tireless three-step routine billions of times a second, fetching an instruction, decoding it, then carrying it out. Understanding that cycle, and the small set of registers and units that perform it, is the key to explaining how any program runs.
In this lesson you will learn the role of the CPU and the microprocessor, walk through the fetch-decode-execute cycle component by component on a Von Neumann machine, and see how cores, cache and clock speed change performance. You will also meet the instruction set and the embedded systems that quietly run the devices around you.
Awọn Afojusun
- 1 (a) Understand the role of the central processing unit (CPU) in a computer (b) Understand what is meant by a microprocessor
- 2 (a) Understand the purpose of the components in a CPU, in a computer that has a Von Neumann architecture (b) Describe the process of the fetch-decode-execute (FDE) cycle, including the role of each component in the process
- 3 Understand what is meant by a core, cache and clock in a CPU and explain how they can affect the performance of a CPU
- 4 Understand the purpose and use of an instruction set for a CPU
- 5 Describe the purpose and characteristics of an embedded system and identify devices in which they are commonly used
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Káàdì ìrántí
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Ìdánwò Ẹ̀kọ́
Oriire fun ipari ẹkọ lori Computer Architecture. Ni bayi ti o ti ṣawari naa awọn imọran bọtini ati awọn imọran, o to akoko lati fi imọ rẹ si idanwo. Ẹka yii nfunni ni ọpọlọpọ awọn adaṣe awọn ibeere ti a ṣe lati fun oye rẹ lokun ati ṣe iranlọwọ fun ọ lati ṣe iwọn oye ohun elo naa.
Iwọ yoo pade adalu awọn iru ibeere, pẹlu awọn ibeere olumulo pupọ, awọn ibeere idahun kukuru, ati awọn ibeere iwe kikọ. Gbogbo ibeere kọọkan ni a ṣe pẹlu iṣaro lati ṣe ayẹwo awọn ẹya oriṣiriṣi ti imọ rẹ ati awọn ogbon ironu pataki.
Lo ise abala yii gege bi anfaani lati mu oye re lori koko-ọrọ naa lagbara ati lati ṣe idanimọ eyikeyi agbegbe ti o le nilo afikun ikẹkọ. Maṣe jẹ ki awọn italaya eyikeyi ti o ba pade da ọ lójú; dipo, wo wọn gẹgẹ bi awọn anfaani fun idagbasoke ati ilọsiwaju.
- Which register holds the address of the next instruction to be processed? A. MDR B. CIR C. Program counter (PC) D. Accumulator Answer: C
- What are the three stages of the cycle a CPU uses to process an instruction? A. read, write, store B. fetch, decode, execute C. input, process, output D. open, run, close Answer: B
- Which component performs the mathematical and logical operations? A. Control unit B. Arithmetic logic unit (ALU) C. Memory address register D. Program counter Answer: B
- Increasing the number of cores in a CPU improves performance mainly because it can: A. store more data permanently B. run more fetch-decode-execute cycles at the same time C. increase the clock speed automatically D. reduce the size of the instruction set Answer: B
- Which is the best example of an embedded system? A. a desktop PC B. a laptop C. the controller inside a washing machine D. a cloud server Answer: C
Ṣiṣẹ́ lórí àwọn ìbéèrè wọ̀nyí nínú ohun èlò náà
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Awọn Iwe Itọsọna Ti a Gba Nimọran
Ẹ̀kọ́ síwájú láti àwọn orísun ṣíṣí
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Abala ìwé ẹ̀kọ́
Computer Levels of Abstraction
"Introduction to Computer Science: Computer Levels of Abstraction" by OpenStax, OpenStax, Rice University, licensed under CC BY-NC-SA 4.0 (https://creativecommons.org/licenses/by-nc-sa/4.0/). Source: https://openstax.org/books/introduction-computer-science/pages/5-2-computer-levels-of-abstraction. Access for free at https://openstax.org/books/introduction-computer-science/pages/1-introduction
Àwọn àjọ mìíràn ló tẹ̀ wọ́n jáde lábẹ́ ìwé àṣẹ ṣíṣí, a sì dá wọn lọ́lá bí wọ́n ṣe béèrè. Àwọn ìjápọ̀ ń ṣí ojú òpó wọn.
Ṣe Adaṣe Awọn Ibeere Idanwo Adaṣe
Ṣe o fẹ ṣe adaṣe awọn ibeere idanwo adaṣe nipa Computer Architecture? Ṣe igbasilẹ ohun elo Green Bridge CBT lati wọle si awọn ibeere idanwo adaṣe ati awọn ayẹwo adaṣe kikun fun koko-ọrọ yii.
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Gbogbo ohun ti o nilo lati ṣe dara julọ ninu JAMB, WAEC ati NECO.
